"Intuition will tell the thinking mind where to look next"   
​                                                                                            - Jonas Salk

  1. US 10,622,956, “Signal level detection and overrange signal limiter and clamp for electronic circuits”
  2. US 10,547,319, “Background calibration of reference, DAC, and quantization non-linearity in ADCs”
  3. US 10,659,069, “Background calibration of non-linearity of samplers and amplifiers in ADCs”
  4. US 10,763,878, “Calibrating time-interleaved switched-capacitor track-and-hold circuits and amplifiers”
  5. US 20190273505, “Background calibration of random chopping non-idealities in data converters”
  6. US 20190296756, “Low power amplifier structures and calibrations for the low power amplifier structures”
  7. US 10,608,654, “Track and hold circuits for high speed and interleaved ADCs”
  8. ​US 20190173481, “Multi-input data converters using code modulation”
  9. US 10,498,303, “Signal level detection and overrange signal limiter and clamp for electronic circuits”
  10. US 9,602,121, "Background estimation of comparator offset of an analog-to-digital converter"
  11. US 9,425,797, "High performance reconfigurable voltage buffers"
  12. US 9,397,682, "Reference buffer with wide trim range"
  13. US 9,276,534, “High speed amplifier”
  14. US 9,276,532, “High speed amplifier”
  15. US 9,184,758, “System and method of analog-to-digital converters”
  16. US 8,872,680, “Calibrating timing, gain and bandwidth mismatch in interleaved ADCs using injection of random pulses”
  17. US 8,866,541, “Distortion cancellation in analog circuits”
  18. US 8,836,558, “Method and device for improving convergence time in correlation-based algorithms
  19. US 8,723,707 “Correlation-based background calibration for reducing inter-stage gain error and non-linearity in pipelined analog-to-digital converters”
  20. US 8,604,953 “Calibrating timing, gain and bandwidth mismatch in interleaved ADCs”
  21. US 8,593,181 “Input switches in sampling circuits”
  22. US 8,471,741 “Method and device for reducing inter-channel coupling in interleaved and multi-channel ADCs”
  23. US 8,471,740 “Reducing the effect of non-linear kick-back in switched capacitor networks”
  24. US 8,446,303 “System and method of analog to digital converters”
  25. US 8,390,487 “System and method of analog to digital converters”
  26. US 8,358,228 “Method for modifying the LMS algorithm to reduce the effect of correlated perturbations”
  27. US 8,339,303 “Method for improving the performance of the summing node sampling calibration algorithm”
  28. US 8,339,161 “High performance voltage buffers with distortion cancellation”
  29. US 8,115,518 “Integrated circuit for reducing nonlinearity in sampling networks”
  30. US 8,068,045 “Calibration methods and structures for pipelined converter systems”
  31. US 8,018,254 “Reducing device parasitics in switched circuits”
  32. US 7,830,288 “Fast, efficient reference networks for providing low-impedance reference signals to signal processing systems”
  33. US 7,786,910 “Correlation-based background calibration of pipelined converters with reduced power penalty”
  34. US 7,746,171 “Amplifier networks with controlled common-mode level and converter systems for use therewith”
  35. US 7,728,752 “Residue generators for reduction of charge injection in pipelined converter systems”
  36. US 7,719,452 “Pipelined converter systems with enhanced linearity”
  37. US 7,652,601 “Fast, efficient reference networks for providing low-impedance reference signals to signal processing systems”
  38. US 7,636,057 “Fast, efficient reference networks for providing low-impedance reference signals to signal converter systems”
  39. US 7,414,564 “Enhanced-accuracy converter stages for pipelined signal converter systems”
  40. US 7,279,986 “Buffer amplifiers with enhanced efficiency”
  41. US 7,271,750 “Pipelined converter systems with enhanced accuracy”
  42. US 7,253,686 “Differential amplifiers with enhanced gain and dynamic range”
  43. US 7,221,191 “Signal samplers with enhanced dynamic range”
  44. US 7,215,182 “High-performance, low-noise reference generators”
  45. US 7,173,470 “Clock sources and methods with reduced clock jitter”
  46. US 7,119,584 “Signal samplers and buffers with enhanced linearity”
  47. US 7,034,736 “Processing systems and methods that reduce even-order harmonic energy”
  48. US 7,026,968 “Analog-to-digital converter and method with switched capacitors for reduced memory effect”
  49. US 7,023,281 “Stably-biased cascode networks”
  50. US 6,861,969 “Methods and structures that reduce memory effects in analog-to-digital converters”
  51. US 6,839,009 “Analog-to-digital converter methods and structures for interleavably processing data signals and calibration signals”
  52. US 6,778,126 “Structures and methods that improve the linearity of analog-to-digital converters with introduced nonlinearities”
  53. US 6,778,013 “Buffer amplifier structures with enhanced linearity”
  54. US 6,756,929 “Methods and structures for interleavably processing data and error signals in pipelined analog-to-digital converter systems”
  55. US 6,501,400 “Correction of operational amplifier gain error in pipelined analog to digital converters”
 © Copyright 2016 Ahmed M. A. Ali